With the heightened speeds and enlarged capacities of optical communication networks in recent years, the operating frequency of a microprocessor has become 30 times higher, the operating speed of a hard disk drive 25 times higher, and the transfer rate of the network [Ethernet (registered trademark)] 100 times higher. On the other hand, it is the existing condition that the transfer rate of a PCI (Peripheral Component Interconnect) bus has hardly changed.
In processing the streaming dat a of a dynamic image, audio technology, etc., however, it has been desired to heighten the transfer rate still more.
In input/output interfaces of the next generation as conform to such a further heightened rate in the future, there are the tendency that multiple reflections are intended to be suppressed by adopting a point-to-point interconnection scheme which connects two adjacent LSIs in one-to-one correspondence, and the tendency that a narrow data-width on the order of 8 bits is adopted so as to facilitate the adjustment of a clock skew even at a high operating frequency.
The adoption of the point-to-point interconnections or the narrow data-width makes easy to employ a network structure which controls the transfer of data with a switch LSI centered, and it therefore affords a construction which is suitable for the transfer of the streaming data.
In this case, however, the interface must be operated at a much higher frequency than in a bus interface having a broad data-width.
By way of example, a high-speed input/output circuit which operates at or above 1 GHz is required in order that a data transfer rate being about 10 times higher than in a PCI bus of 32-bit width may be realized using a data bus of 8-bit width.
It is expected that, in order to comply with such a demand for the heightened rate, the quantity of production of LSIs each having a high-speed I/O of LVDS (Low Voltage Differential Signaling) or the like will steadily increase from now on.
Besides, the high-speed I/O includes a multiplexer, a PLL (Phase Locked Loop), or the like. Regarding a test, accordingly, there is necessitated a measure which is different from an LFT (Loose Function Test) or a DC test having hitherto been practiced for an I/O section, that is, an at-speed test.
Even at the present time, in specifications, a probe card itself or the very LSI tester is capable of coping with digital signals which exceed 1 Gbit/second.
However, the whole test system in which the card or the tester is combined is limited to a test for digital signals on the order of 200 Mbits/second to 400 Mbits/second. The circumstances will be explained with reference to FIG. 7.
Reference to FIG. 7:
FIG. 7 is the conceptual constructional view of a prior-art test system. In the prior-art test system, an IC socket 72 is disposed at the central part of a load board 71, lead lines 73 are laid so as to connect to the IC socket 72, and coaxial cables 75 are connected to an LSI tester 74 so as to couple to the lead lines 73.
Besides, using a handler 76, a DUT (Device Under Test) 77 which is a device to-be-tested is set on the IC socket 72 so as to perform a test.
In this case, the magnitudes of wiring lengths (cable lengths) from the DUT 77 to the LSI tester 74 being a waveform detection portion become a problem.
More specifically, in a high frequency signal whose clock frequency is 1 GHz or above, the distortion of a digital waveform appears under the influence of a skin effect which is proportional to the square of a line length, or a dielectric loss which is proportional to the line length. Therefore, in a case where the wiring length from the DUT 77 to the LSI tester 74 being the waveform detection portion is large, it becomes very difficult to detect a digital signal whose clock frequency exceeds 1 GHz.
In such a situation, there has been developed an analog BOST (Built-Out Self-Test) in which a measurement circuit and an analysis circuit for analog signals are mounted on the load board, whereby a general-purpose logic tester is permitted to perform an analog test.
Mentioned as the merits of the BOST are:    that, in the first place, a guarantee with an external interface included is possible;    that, secondly, the area penalty of a chip is not involved; and    that, thirdly, observability in a chip evaluation is high.
When a BOST for an LSI having a high-speed I/O in the future is considered, the first and third merits stated above are conditions indispensable to the test of the high-speed I/O, and the test of the high-speed I/O is permitted by remarkably reducing the wiring length from the DUT to the signal detection portion as indicated before.
Meanwhile, in a semiconductor integrated circuit device (LSI), it has been proposed as a test facilitating design to separate the interior of the LSI into I/Os and internal logic by a boundary scan register. This will be described with reference to FIG. 8.
Reference to FIG. 8:
FIG. 8 is the conceptual constructional view of a semiconductor integrated circuit device which is provided with a boundary scan register. The boundary scan register 83 is disposed at the outer peripheral part of a semiconductor chip 81, thereby to isolate I/Os 84 from internal logic 82 which is constituted by logic circuits, a memory, etc. disposed inside.
Owing to the use of such a boundary scan register, the test of the internal logic is facilitated, and it is simultaneously permitted to designate transmission signals or test reception signals for the high-speed I/Os.
Besides, a logic BIST (Built-In Self-Test) has been proposed as another test facilitating design. This will be described with reference to FIG. 9.
Reference to FIG. 9:
FIG. 9 is the conceptual constructional view of a semiconductor integrated circuit device which adopts a logic BIST. A pseudo-random pattern generator 92 and an output pattern compressor 93 are disposed on a semiconductor chip 91, and the pseudo-random pattern generator 92 and the output pattern compressor 93 are connected by a scan chain 94.
An LSI tester 95 which is disposed outside in this case performs the initial setting of the pseudo-random pattern generator 92, and the obtainment of a result from the output pattern compressor 93.
Besides, unlike in the prior art, a test pattern is not outputted from the LSI tester 95, but it is outputted from the pseudo-random pattern generator 92 included in the LSI. The result of a test in the LSI is sent to the output pattern compressor 93.
Besides, the pseudo-random pattern generator 92 is constructed of, for example, an LFSR (Linear Feedback Shift Register), and the output pattern compressor 93 is constructed of, for example, an MISR (Multiple Input Signature Register), whereby the area penalty of the semiconductor chip 91 can be realized small.
In general, however, the BOST has the demerits:    that, in the first place, the number of pins of the chip is limited; and    that, secondly, a packaging space for packaging the measurement circuit and the analysis circuit is necessary on the load board. Among them, the first demerit poses no problem in the high-speed I/O test, but the second demerit concerning the packaging space needs to be solved.
Further, a problem peculiar to the high-speed I/O test in considering the BOST is adaptations to various specifications including input/output signal levels.
By way of example, in the high-speed I/O test, the BOST has the problem that the various specifications, such as the input/output signal levels [CML (Current Mode Logic), LVDS, etc.] and high-speed signal processing techniques [waveform emphasis (preemphasis), multi-valued transmission, simultaneous bidirectional transmission, etc.], must be conformed to.
On the other hand, the logic BIST has the problem that a test closed within the LSI cannot be performed for testing the I/O portion.
Accordingly, the present invention has for its object to perform the test of a high-speed I/O exceeding 1 GHz, promptly by a simple board construction, without altering a test system for individual I/O specifications.